Various systems and methods are provided for memory mirroring. In one embodiment, a mirror memory is provided having a memory fully buffered controller, the memory fully buffered controller being configured to facilitate access to a plurality of memories in the mirror memory by a central processing unit (CPU). A primary memory link interface configured to couple to a primary memory is provided in the memory fully buffered controller. The memory fully buffered controller further comprises first error logic configured to detect whether a first data error exists in a first data output from the primary memory, and second error logic configured to detect whether a second data error exists in a second data output from the mirror memory. The memory fully buffered controller also comprises selection logic that selects one of the first data output or the second data output to be applied to the CPU.