A mass memory device (1) having a plurality of mass memories (2) and having at least two bridge controllers (3) which are coupled to the mass memories (2) by a data bus. A first common cache memory unit (4) is provided, to which the bridge controllers (3) are connected by means of an additional cache synchronization system for the purpose of storing and synchronizing data which are to be stored. A method is provided for operating a mass memory device (1) having a plurality of mass memories (2) and having at least two bridge controllers (3) which can be used to address the mass memories (2), and at least one first common first common cache memory unit (4) which is associated with the bridge controllers (3). All data to be stored are initially stored on the first common cache memory unit (4) and are automatically mirrored on an optional further common cache memory unit (4). The data initially stored in the first common cache memory unit (4) are transferred to the mass memories (2) for storage therein.