Methods, systems and computer program products for automatically minimizing leakage current in a circuit design can include post layout delay information of a circuit that meets timing limits is analyzed. The circuit can include a first type of cells, and the first type of cells each can include a first threshold voltage and a first leakage current. After post layout delay information are analyzed, a non-speed-critical path in the circuit is selected. A dopant implant level of at least one transistor in at least one cell along the selected non-speed-critical path is modified to change the first threshold voltage of the transistor to a second threshold voltage and the first leakage current of the transistor to a second leakage current. In some implementations, the magnitude of the first threshold voltage is less than a magnitude of the second leakage current and the total leakage current of the circuit is reduced.