A central processor executes at least a load command, a store command, and a prefetch command based on an out-of-order processing for processing commands by changing the order of executing the commands. A valid move-in buffer (MIB) detector detects the number of primary cache MIBs that hold requests of a primary cache for reference to data stored in the main storage. An MIB controller controls to hold in the primary cache MIBs the reference requests according to the load command or the store command in preference to the reference requests according to the prefetch command, when the detected number of the cache buffers reaches a predetermined number.