An integrated memory includes a circuit for testing the operation of the
memory, a register circuit is used for storing a bit combination,
compression unit, to receive test data which have been read from the
memory cells, and a memory unit to store a plurality of bits from a
compressed bit fail map. Each of the bits is associated with a different
address region. One of the bits registers an error data item within the
associated address region. In addition, a decoder circuit is provided for
receiving the compressed address and for accessing that bit in the memory
unit, which is associated with a respective address region on the basis
of the compressed address. A short evaluation time for a function test on
the memory and flexible alignment with the individual memory size are
made possible.