Techniques for designing integrated circuits (ICs) with optimization at
register transfer level (RTL) amongst multiple ICs are described herein.
According to one embodiment of the invention, a hierarchical resource
estimation is performed based on a technology independent register
transfer level (RTL) netlist, which is to be partitioned between multiple
ICs. Based on the estimation, the RTL netlist is partitioned between the
multiple ICs. In response to the partition and the estimation, immediate
feedback information is provided to a user.