A method for accurately determining the provisional quantity and provisional locations of power supply pads prior to detailed layout of a semiconductor integrated circuit. The method decreases redesigning, shortens the design time, and lowers design costs. The method includes performing a power supply network analysis of the core section to obtain voltage values of the nodes, calculating current values between the nodes from the voltage values of the nodes and the resistances between the nodes, and calculating current values of the power supply pads from the current values between the nodes. The method further includes determining whether to eliminate or add a power supply pad depending on whether the current value of each power supply pad exceeds the current capacity of an associated IO buffer.