A method and digital processor to process digital samples is provided. The processor may comprise a time domain processing engine to process a digital sample in the time domain, and a frequency domain processing engine to process a digital sample in the frequency domain. Shared memory is provided in the digital processor with which time domain and frequency domain processed samples are exchangeable. The time domain processing engine may processes data samples in a sample-by-sample manner and the frequency domain processing engine may processes data samples in a block-based manner. The processing engines may be integrated in a single DSP chip. In one embodiment, an interrupt generator is provided that generates an interrupt and an input buffer communicates an input data sample to the processor in response to the interrupt and the output buffer communicates an output data sample to the digital sample bus in response to the interrupt.