An estimate of the throughput of a multi-threaded processor based on
measured miss rates of a cache memory associated with the processor is
adjusted to account for cache miss processing delays due to memory bus
access contention. In particular, the throughput calculated from the
cache memory miss rates is initially calculated assuming that a memory
bus between the cache memory and main memory has infinite bandwidth, this
throughput estimate is used to estimate a request cycle time between
memory access attempts for a typical thread. The request cycle time, in
turn, is used to determine a memory bus access delay that is then used to
adjust the initial processor throughput estimate. The adjusted estimate
can be used for thread scheduling in a multiprocessor system.