Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry coupled to target logic under test, where the test circuitry is configured to perform logic tests on the target logic using input data and thereby generate signature data. The system includes a first number of I/O ports that are shared for input and output and alternately convey the input data to the test circuitry and output the signature data generated by the test circuitry. The signature data includes a second number of bits greater than the number of I/O ports. The test circuitry is configured in a first mode to successively output multiple segments of the signature data through the I/O ports, where each segment has a number of bits no greater than the number of I/O ports.