A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.