A processor-implemented method is provided for comparing connections in a
graphical representation of a programmable logic device (PLD) design to
connections in a netlist that describes the PLD design. The netlist and
an identification of each tile are input. For each of the tiles, a
specification is input of a graphical tile representation and connection
representations that terminate at a boundary of the tile representation.
A specification is input of an arrayed placement of occurrences of the
tile representations. For each abutting pair of occurrences of the tile
representations in the arrayed placement, the connection representations
are determined that terminate at a shared portion of the boundaries of
the tile representations of the abutting pair. For each of a plurality of
positions within the shared portion of the boundaries of the tile
representations of each abutting pair, a match is checked between the
connection representations terminating at the position.