A digital camera is provided with a data amount detector and a clock control circuit. The data amount detector detects the amount of image data stored in an SDRAM in capturing a moving image. The clock control circuit controls a transfer speed of the image data from the SDRAM to a memory card by changing a frequency of a system clock based on the detecting result from the data amount detector. When the data amount is less than a first threshold value set near a lower limit of a memory capacity of the SDRAM, the clock control circuit reduces the data transfer speed by lowering the frequency of the system clock; meanwhile, the data amount is more than a second threshold value set near an upper limit of the memory capacity of the SDRAM, the clock control circuit accelerates the transfer speed by raising the frequency of the system clock.