A refresh control circuit and method thereof and a bank address signal change circuit and methods thereof. The bank address signal change circuit may receive bank address signals from a bank address signal generation circuit. The received bank address signals may designate a first at least one of a plurality of memory banks. The bank address signal change circuit may determine whether the first at least one designated memory bank is associated with the longest refresh cycles from among the plurality of memory banks. Based on the determination, the bank address signal change circuit may generate a plurality of bank address signal change signals designating a second at least one of the plurality of memory banks. A refresh operation circuit may perform a refreshing operation on the second at least one memory banks in accordance with the bank address signal change signals. The bank address signal generation circuit, bank address signal change circuit and refresh operation circuit may each be included in a refresh control circuit.