A data processing system includes at least first and second coherency
domains, each including at least one processor core and a memory. In
response to an initialization operation by a processor core that
indicates a target memory block to be initialized, a cache memory in the
first coherency domain determines a coherency state of the target memory
block with respect to the cache memory. In response to the determination,
the cache memory selects a scope of broadcast of an initialization
request identifying the target memory block. A narrower scope including
the first coherency domain and excluding the second coherency domain is
selected in response to a determination of a first coherency state, and a
broader scope including the first coherency domain and the second
coherency domain is selected in response to a determination of a second
coherency state. The cache memory then broadcasts an initialization
request with the selected scope. In response to the initialization
request, the target memory block is initialized within a memory of the
data processing system to an initialization value.