Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al.sub.2O.sub.3, Ta.sub.2O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2O.sub.5, SrBi.sub.2Ta.sub.2O.sub.3, SrTiO.sub.3, PbTiO.sub.3, and PbZrO.sub.3.