A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.