A technique for reducing off-chip bandwidth requirements for a processor reads old data from a location in an on-chip store of a processor in preparation of writing new data to the location in the on-chip store. The technique determines whether new data bytes of the new data and associated old data bytes of the old data are different. The new data bytes are then written to the on-chip store. When updating an off-chip store, only the new data bytes that are different are written to the off-chip store. In this manner, off-chip bandwidth requirements for a processor may be reduced.