An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence. Each level representsmg a logic value consisting of a plurality of bits, wherein the structure includes components for detecting errors in the values of a selected block of memory cells. The structure further includes components for partitioning the bits of each memory cell of the block into a first subset and a second subset, the bits of the first subset being unchanged in the values of a first and a second ending range in the sequence. The components_for detecting errors only operate on the bits of the second subset of the block.