A microprocessor coupled to a system memory includes a load request signal that requests data be loaded from the system memory into the microprocessor in response to a load instruction. The load request signal includes a load virtual page address. The microprocessor also includes a prefetch request signal that requests a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction. The prefetch request signal includes a prefetch virtual page address. The microprocessor also includes a memory subsystem including a first translation look-aside buffer (TLB) that translates the load virtual page address into a load physical page address, a second TLB that translates the prefetch virtual page address into a prefetch physical page address, and a third TLB that translates the load virtual page address into the load physical page address if the load virtual page address misses in the first TLB and translates the prefetch virtual page address into the prefetch physical page address if the prefetch virtual page address misses in the second TLB.