Circuits, methods, and apparatus that increase utilization of available USB bandwidth, limit the amount of data accessed from memory, and provide for parallel requests for data from memory. An exemplary embodiment of the present invention caches a pointer for each transfer descriptor in a periodic and async schedule. Several transfer descriptors are also cached. Caching pointers reduces the time needed to organize the needed transfer descriptors to be transmitted. Caching several transfer descriptors eliminates the need to access the main memory each time they are needed. Also, if more transfer descriptors are needed beyond those in cache, memory requests for multiple transfer descriptors may be done in parallel since their pointers are available in cache.