Disclosed is a hardware architecture receiving multi-input blind source signals and obtaining multi-output. An apparatus for separating blind source signals includes: a forward process unit receiving a plurality of blind source signal vectors and outputting a plurality of output signal vectors by using a predetermined blind source separation algorithm; an update process unit receiving the plurality of output signal vectors and learning first weighting values used for the predetermined blind source separation algorithm according to a predetermined learning algorithm; and a weight process unit having a matrix operation structure for receiving the first weighting values and converting them into coefficients and second weighting values applicable to the predetermined blind source separation algorithm. The forward process unit includes (L+1) identical processing elements connected in a systolic array structure, where L is the number of sequential delay of blind input signal vectors. The update process unit includes (N.sup.2+N)/2.times.(2L+1) identical updating elements connected in a systolic array structure, where N is the number of the blind input signal vectors. Each cost of the processing elements and the updating elements is initialized by 0 in an initial operation stage.