A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor processor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface. Also, included is a system having a display controller with an asynchronous bus interface and methods for performing read and write operations between a microprocessor and a display controller.