A processor is provided that includes decode logic coupled to an instruction cache and a micro-sequence vector table including entries for each bytecode in an instruction set of the processor. The processor also includes a register coupled to the decode logic, wherein the register is dedicated for storage of an immediate operand of a bytecode. The decode logic is configured to obtain a single bytecode from the instruction cache, wherein the single bytecode requires an immediate operand stored in the instruction cache, use the single bytecode to locate an entry corresponding to the bytecode in the micro-sequence vector table, and, when indicated by information in the entry, obtain the immediate operand from the instruction cache and store the immediate operand in the register for use by a micro-sequence that is executed in lieu of the single bytecode.