A multi-phase converter comprising a plurality of switching circuits each providing a switched voltage to an output node of the converter and wherein each switching circuit sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed; a clock circuit for providing a plurality of out of phase clock signals to the switching circuits to determine when each switching circuit provides the switched voltage to the output node; each switching circuit comprising first and second series connected switches connected across a DC voltage bus; further comprising a first circuit comparing a first signal proportional to a difference between the output voltage of the converter at the output node and a first reference voltage with a second signal comprising a ramp signal and for producing a pulse width modulated signal to control the on-times of the switches of the connected switching circuit; further comprising a second circuit comparing the first signal proportional to the difference between the output voltage and the first reference voltage to a second reference voltage and if the first signal exceeds the second reference voltage by a prescribed amount, for turning on at least one switching circuit to provide the switched output voltage to the output node prior to occurrence of the clock signal.