A source synchronous external memory device returns data to a memory
controller of an electronic device with its own clock signal, which
allows the returned data to be captured with a high degree of accuracy.
The captured data must then be resynchronized with the clock signal which
controls the other components of the electronic device. This problem is
particularly acute in the case of high speed memory devices, such as DDR
(Double Data Rate) memory devices, and similar memory devices. Test data
is written to the external memory device, and is then read back several
times. Attempts are made to resynchronize the captured data with the
system clock, with different relative variations in the phase of the
captured data and the system clock, in order to select a value for the
relative phase, which allows for optimum resynchronization.