A method for controlling operation of a secure execution mode-capable processor includes receiving access requests to a plurality of addressable locations within a system memory. The method may further include preventing the access requests from completing in response to determining that the secure execution mode-capable processor is operating in a secure execution mode.

 
Web www.patentalert.com

< Asynchronous jitter reduction technique

> Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

> Accessing protected resources via multi-identity security environments
~ 00500