A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure. A drain region and a source/base region are formed in the semiconductor substrate adjacent the first gate structure and a cathode region is formed in the semiconductor substrate adjacent the second gate structure. The drain region, the source/base region, and the cathode region have a second conductivity type. An anode region of the first conductivity type is formed adjacent the second gate structure in a portion of the source/base region.