A sequential cell is characterized using interdependent setup/hold time
pairs to produce associated clock-to-Q delay values, and then identifying
setup/hold time pairs that produce a selected clock-to-Q delay value
(e.g., 10% of failure). The identified setup/hold time pairs (or a
piecewise linear (PWL) approximation thereof) are then stored in a cell
library for use in static timing analysis (STA). During STA, the setup
and hold skews calculated for each synchronous circuit are compared with
a selected setup/hold time pair stored in the cell library (e.g., a pair
having a relatively low hold value). If at least one of the setup and
hold skews violates the selected setup/hold time pair, then the remaining
identified setup/hold time pairs (or the PWL approximation) are utilized
to determine if the synchronous circuit is violates established
constraints, and if not, to identify the setup and hold times required to
remove the violation.