A system and method for determining whether a desired integrated circuit
layout can be accurately modeled from a resist model that is calibrated
from a mask test pattern. In one embodiment, a chessboard graph is
created having horizontal and vertical axes that are assigned two imaging
parameters calculated from the test mask data and the desired integrated
circuit layout data. Data on the horizontal and vertical axes of the
chessboard graph are divided into a number of ranges or bins. The
intersection of each bin on the horizontal and vertical axis is
associated with a subgraph that plots the relation between two additional
imaging parameters having values of the first two imaging parameters in
the ranges of the intersecting bin.