Disclosed is a frequency synthesizer capable of preventing occurrence of a frequency shift upon occurrence of a change in the level of an input to an A/D converter by preventing PLL control from being properly operated. The frequency synthesizer includes a carrier remove, an inverse rotational vector multiplier, a phase time difference detector, an adder, a phase difference accumulator, a loop filter, a parameter output part, an amplitude information detector, a filter, and a multiplier configured by an FPGA. Unlock detection means monitors the value of amplitude information detected by the amplitude information detector. When the value lies within a proper range, a lock (synchronization) process is performed under PLL control, whereas when the value is off the proper range, an unlock state in PLL control is detected.