An apparatus and method for efficiently managing data cache load misses is
described in connection with a multithreaded, pipelined multiprocessor
chip. A CMT processor keeps track of load misses for each thread by
issuing a load miss signal each time a load instruction to the data cache
misses. A detection logic functionality in the IFU responds the load miss
signal to determine if a valid instruction from the thread is at the one
of the pipeline stages. If no instructions from the thread are detected
in the pipeline, then no flush is required and the thread is placed in a
wait state until the requested data is returned from higher order memory.
If any instruction from the thread is detected in the pipeline, the
thread is flushed and the instruction is re-fetched.