A (binary) signal is transmitted through an electrical backplane, and the received signal is interpreted as a duobinary signal. In order to ensure that the received signal can be properly interpreted as a duobinary signal, the data signal is preferably filtered prior to being interpreted. The filter is preferably designed such that the combination of filter and the backplane approximates a binary-to-duobinary converter. In one embodiment, an (FIR-based) equalizing filter is applied to the data signal prior to transmission to emphasize the high-frequency components and flatten the group delay of the backplane. The resulting, received duobinary signal is converted into a binary signal by (1) splitting the duobinary signal, (2) applying each copy to a suitably thresholded comparator, and (3) applying the comparator outputs to a suitable (e.g., XOR) logic gate. The transmission system enables high-speed data (e.g., greater than 10 Gb/s) to be transmitted over relatively inexpensive electrical backplanes.