A computerized device having a first processing device, a second processing device, and an interconnection mechanism allowing communication between the first and second processing devices, provides a mechanism for testing a processing device by performing the isolation and testing operations of operating the first processing device in a normal processing mode and transitioning the first processing device from the normal processing mode to an isolated processing mode. The device performs a test process on the first processing device while in isolated processing mode to test functional portions of the first processing device. If operation of the test process produces an error in a functional portion of the first processing device, the test process notifies a control process on a second processing device of the error in the functional portion of the first processing device in which the test process produced an error. If operation of the test process does not produce an error in the functional portions of the first processing device, the device transitions the first processing device from the isolated processing mode back to the normal processing mode upon completion of the test process. The process can be repeated periodically on all processors in a device at an interval that is less than an average mean time between failures of the processing devices.