A network processor or other type of processor includes clock generation circuitry which generates one or more clock signals for each of a number of clock domains of the processor. The clock generation circuitry comprises at least one clock generator and at least one control register subject to software-based updating. The clock generation circuitry determines a first clock configuration for the processor based on sampling one or more external clock configuration signal lines of the processor, and configures the clock generator in accordance with the first clock configuration. The clock generation circuitry subsequently determines a second clock configuration for the processor, different than the first clock configuration, based on contents of at least one control register subject to software-based updating, and reconfigures the clock generator in accordance with the second clock configuration.