A clock and data recovery circuit includes even and odd latches, a detection module, a clock recovery module, a compensating module, and a data recovery module. The even and odd latches are operably coupled to latch even and odd bits of a digital stream of data based on a recovered clock to produce even and odd latched bits. The detection module is operably coupled to produce a phase representative pulse stream based on the even and odd latched bits. The clock recovery module is operably coupled to produce the recovered clock based on the phase representative pulse stream. The compensating module is operably coupled to adjust biasing of the even and odd latches based on operating parameter changes of the clock and data recovery circuit. The data recovery module is operably coupled to produce recovered data from the even and odd latched bits based on the recovered clock.