A computer having a CPU which operates with at least two operation modes,
comprising: a mode signal output unit outputting an operation mode signal
corresponding to the operation mode of the CPU; a CPU power supply
supplying power having a voltage level corresponding to the operation
mode signal outputted from the mode signal output unit to the CPU; and a
control unit controlling the CPU power supply to decrease an equivalent
series resistance value to power outputted from the CPU power supply for
a predetermined period of time for delay from when switching the
operation mode of the CPU has been sensed, based on the operation mode
signal outputted from the mode signal output unit.