An output of a first ring counter is held in a first storage circuit. Outputs of a second ring counter and the first storage circuit are input to a first AND circuit group. An output of a third ring counter and an output of the first storage circuit are input to a second AND circuit group. Outputs of the first AND circuit group are input to a first OR circuit. Outputs of the second AND circuit group are input to a second OR circuit. An output of the first OR circuit is stored in a second storage circuit. An output of the second OR circuit is stored in a third storage circuit. Outputs of the first and second OR circuits and outputs of the second and third storage circuits are supplied to a decode circuit, and are decoded to output an overflow signal and an underflow signal.