An automatic frequency correction phase-locked loop (PLL) circuit includes
an analog control circuit and a digital control circuit. The digital
control circuit includes a High-side comparator and a Low-side comparator
which receive an analog control voltage, a state monitor circuit, and a
counter and decoder circuit. At least one of the High-side comparator and
the Low-side comparator includes a threshold switching circuit which
selectively provides a first threshold voltage and a second threshold
voltage, the first and second threshold voltages having different
magnitudes. When the analog control voltage remains stable between the
High-side threshold voltage and the Low-side threshold voltage and the
threshold switching circuit is providing the first threshold voltage, the
state monitor circuit switches the threshold switching circuit from the
first threshold voltage to the second threshold voltage, thereby
expanding the interval between the High-side threshold voltage and the
Low-side threshold voltage.