A system and a method for cache coherence are provided. The system
includes a memory apparatus, a detector, a plurality of access-consumers
and a plurality of pass-gates. At least one of the access-consumers is a
processor having a cache. When the processor replaces the first data in
cache with the second data read from the memory apparatus, the process
issues the read second data request first, followed by the write-back
first data request. The detector provides a detecting signal when the
processor issues the read second data request and cancels the provided
detecting signal when the processor issues the write-back first data
request. Each pass-gate decides whether to pass the third access request
outputting from each corresponding access-consumer and transmit it to the
memory apparatus according to the detecting signal respectively.