A thin film transistor array substrate including a gate pattern having a gate electrode, a gate line connected to the gate electrode, and a gate pad connected to the gate line, a source/drain pattern having a source electrode, a drain electrode, a data line connected to the source electrode, and a data pad connected to the data line, a gate insulating pattern formed along a matrix pattern including the gate pattern and the source/drain pattern except for a pixel area, a semiconductor pattern formed on the gate insulating pattern having a same pattern as the gate insulating pattern and partially removed at a thin film transistor area and the gate line area, and a transparent electrode pattern having a pixel electrode formed at the pixel area and connected to the drain electrode, a gate pad protective electrode formed on the gate pad, and a data pad protective electrode formed on the data pad.