Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture. The memory device includes: a plurality of word lines and a plurality of bit lines each regularly arranged, and a plurality of unit memory cells each formed at an intersection between an associated one of the word lines and an associated one of the bit lines, wherein each unit memory cell includes a capacitor connected to one of the bit lines and a threshold voltage switching device comprising two terminals, one terminal being connected to the capacitor and the other terminal being connected to one of the bit lines, the threshold voltage switching device being capable of switching current flow at a specific threshold voltage via a rapid variation in resistance depending upon a voltage applied through the word line and the bit line, wherein the capacitor is capable of accumulating electric charges supplied from the bit line based on a switching operation of the threshold voltage switching device.