Controlling a bitline bias voltage by sensing the bitline bias voltage, modifying a bitline bias control signal in accordance with the sensed bitline bias voltage, and controlling the bitline bias voltage in accordance with the modified bitline bias control signal. The modifying the bitline bias control signal is carried out by enabling a pull up circuit and disabling a pull down circuit in response to a first control signal and disabling the pull up circuit and enabling the pull down circuit in response to a second control signal.

 
Web www.patentalert.com

< Method of high-performance flash memory data transfer

> Method for using a reversible polarity decoder circuit

> Methods for optimizing page selection in flash-memory devices

~ 00516