A test environment for performing verification on a parameterizable circuit design can include a test harness specifying a first instance of a device under test characterized by a first parameterization and at least a second instance of the device under test characterized by at least a second parameterization. The test environment further can include a hardware verification language shell configured to randomly generate signals which indicate one of the instances and provide the signals to the test harness. The test harness selects one of the instances according to the signals.