In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal. The phase aligner also stores the second data source signal in response to the second frame source signal and the second clock source signal. The phase aligner aligns a phase of the first data source signal with a phase of the second data source signal in response to the recovered reference signal and the recovered clock signal.