A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.