Al.sub.xIn.sub.yGa.sub.1-x-yN (0.ltoreq.x.ltoreq.1; 0.ltoreq.x.ltoreq.1; 0.ltoreq.x+y.ltoreq.1) layered device chips are produced by the steps of preparing a defect position controlled substrate of Al.sub.xIn.sub.yGa.sub.1-x-yN (0.ltoreq.x.ltoreq.1; 0.ltoreq.y.ltoreq.1; 0.ltoreq.x+y.ltoreq.1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S. Chip-separation is done instantly by the high power laser irradiation or mechanical shock without cutting the substrate S. The defect position controlled substrate S is repeatedly reused.