A memory storage device connectable to a bus comprises a first memory module that stores data, a second memory module that is capable of being programmed, and a memory controller that communicates with the first memory module, the second memory module, and the bus, and that determines an address mapping of selected areas of the first memory module onto the second memory module. When the memory controller receives an access request from the bus, the memory controller accesses data from the first memory module unless the address mapping specifies that the access request maps to the second memory module, whereupon the memory controller accesses replacement data from the second memory module.