In an image signal processor with which a group of control variables, having relevance to one another, stored in registers are activated synchronously with the switching of a picture, when a host sets the control variable group in the registers, mutual coherency is secured even if the setting operation extends beyond a pulse of a vertical synchronous signal (VD). In order to realize this, an operation for setting a control variable group in a register block (20) by the host, and an operation for reflecting the control variable group in a DSP block (22), are separately performed. After setting of the control variable group, the host sets H level in a VLAT register (30). In correspondence with this operation, a control portion (24) updates an output of a latch circuit (36). As a result, the control variable group is activated from the register block (20) to the DSP block (22).