A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.